Task 8 and 9: Oxide Charge Density and Comparison

We finished Task 8 and 9 this Friday. We know that Q=C_ox*ΔV, whereΔV is the shift of CV plot. ΔV can be recognized as the difference between gate voltage(V_G) and oxide voltage(V_o). The equation shown below can be used to calculate gate voltage.

Flatband Condition (work function difference needed)

Under this circumstance, the gate voltage is 0V and we don’t need the foregoing equation. The equation of Q can be simplified as Q=C_ox*(-V₀). Since V₀=V_FB-V_MS, use the results of Task 5 and 6, it’s easy to find out that V₀=0.455V. Finally, total charge and charge density are equal to -5.17*10^-7C/cm² and -3.23*10¹²cm^-2 respectively.

Midgap Condition (work function difference ignored)

In this condition, surface potential is equivalent to Fermi energy. Plug all data in the equation and gate voltage is 0.327V. Task 7 provides midgap voltage which is 1.23V andΔV should be -0.902V. Eventually, total charge in this area is -6.4*10¹²cm^-2 and its density is -1.0242*10^-6C/cm².

Comparison

We just shared and compared the data with the group who did the project slightly different from us. This task asks us to explain the reason why relative permittivity drops with Hafnium percentage in oxide. Two groups were all agree with the explanation shown below. High-k dielectrics have much higher relative permittivity than silicon dioxide and since the amount of Hafnium decreases (equivalent to increasing of silicon dioxide), whole permittivity of diode inevitable drop.

Task 7: Midgap Voltage

On the Midgap condition, depletion capacitor is in series with C_0x. We have already known C_0x was the maximum capacitance of the gate and the depletion capacitance could be deduced by the equation shown below. Under this circumstance, the work function of semiconductor Φs is equal to Fermi energy Φ_F. Therefore, the total capacitance is approximately 69.3pF and the voltage is between 1.21 and 1.22 volts.

Task 6: Flatband Voltage

The flat band voltage of MOSFET is influenced by the oxide-semiconductor interface and the voltage which when applied to the gate electrode yields a flat energy band. The charge in the oxide or at the interface changes this flatband voltage.As the plot below displays, the capacitance of the flatband would equal to the series of C_ox and C_D.

Firstly, we need to calculate the Debye length which would be 

For ε₀=8.85×10^-12F/m

  ε_s=11.7

kT_t/q=0.026V

N_D=2.7×10²¹

Therefore, L_D =78nm.

Aftwewards, we would calculate the C_D, which is semiconductor capacitance

For For ε₀=8.85×10^-12F/m

ε_s=11.7

L_D=78nm

A=π(d/2)² ,where d=0.58nm

Therefore,C_D=350pF

Finally, we carried out the formula of capacitors in series, and achieved

C_FB=314pF

Then, we find the corresponding voltage in the plot in task 1 and find out the rough voltage is 0.52V.

Task 5: Work Function Difference with Gold Gate

We worked on Task 5 to 7 this Friday at the computer lab. This blog will introduce Task 5. The figure shows below is about energy band diagram for gate. Work function is the minimum energy cost of moving an electron from Fermi level to infinity. In this case, the work function difference is equivalent to Φ_M-Φ_S, where Φ_S is X(Si)+E_g/2+Φ_F. Table 1 shows the meanings of different variables.

Figure 1: Energy Band Diagram

ΦM	The work function of metal;
ΦS	The work function of semiconductor;
X(Si)	Electron Affinity;
Eg	Bandgap energy;
ΦF	Fermi energy.

Table 1: The meanings of Variables

Task 2 and 3: Relative Permittivity and Equivalent Oxide Thickness

Relative Permittivity

From Task 1 we know that the when the gate is in accumulation condition, the total capacitance is 3000pF. Under this circumstance, the accumulation capacitor, C_SiO2 and C_High-k are in series. Due to a high value of accumulation capacitor, it could be ignored. Therefore, we deduced that C_max=C_SiO2||C_High-k. Since we also know that C=Aε₀ε_r/t, where t is the thickness of material; the only one unknown value is ε_High-k (ε_r). Hence we got ε_r is about 8.67.

Equivalent Oxide Thickness (EOT)

Once we knew the relative permittivity of High-k material, it was easier to determine EOT. According to the equation EOT=ε_SiO2*t_{High-k /}ε_r+t_SiO2, EOT can be calculated as 3.04nm.

Task 4: Doping Density of the Silicon Substrate

There are still some problems about Task 2 and 3; therefore, we decide to introduce Task 4 before them.

After studying for several minutes, we found a complex equation about doping density as shown below. 

A	Area of capacitor;
k	Boltzmann’s constant: 1.38*10-23J/K;
T	Temperature: normally choose 300K;
q	The minimum charge quantity: 1.6*10-19C
e0	Permittivity of vacuum: 8.85*10-12F/m;
es	Relative permittivity: In this case we choose 13.9 (Si);
C	Capacitance: 48pF ~ 3nF;
ND	Intrinsic carrier concentration: We normally use 1016m-3 at 300K.

Table 1: The Meanings of Variables 

After simplifying the equation, we got N_D/(2.14*10²⁰)=ln(N_D/10¹⁶). Let’s just recognize N_D/(2.14*10²⁰) as part one and the right hand side as part two. As always do, we used two methods to calculate.

First Method

We just applied formula in Matlab to solve the equation and the answer is shown below. It seems that the equation has two solutions, however, one answer exceed the limit. The solution 10¹⁶ indicates that the substrate was not doped and it did not fit the condition we got. Therefore this answer was abandoned.

Figure 1: Answers to equation

Second Method

Although we have already known that the solution 10¹⁶ m^-3 was not we needed, we still plotted part one and two in one graph between 10¹⁵ and 10¹⁷. From Figure 2 we know that the calculation for first answer was right.

Figure 2: The First Answer to Equation

Then we did some calculations and found that another solution was from 10²¹ to 10²². We plotted the images between 10²¹ and 10²² and the solution that we want is approximately 2.7*10²¹ m^-3.

Figure 3: The Second Answer to Equation

Task 1: Determine the type of substrate

We received related data from Dr. Ivona last week and finished the first four tasks before the end of last week. This blog mainly explained the first task- identify the type of substrate. Figure 1 [1] illustrates C-V character of p-type material at high frequency. We were planning to find the C-V character from data and to verify if the curve of the material coincide to C-V character of p-type.

Figure 1: C-V character of p-type material

We first plotted C (capacitor) versus V (voltage) by using the data. The plot was performed in the MATLAB software. In order to ensure the plot is correct, data was also applied into Microsoft Excel.

The two screenshots of result are shown below. It is obvious that the material we got is p-tpye.

Figure 2: C vs V (MATLAB)

Figure 3: C vs V (Microsoft Excel)

[1] Keithley (2007) ''C-V Characterization of MOS Capacitors Using the Model 4200-SCS Semiconductor Characterization System'' [online]. Available: www.keithley.co.uk/data?asset=50977. [Accessed: Feb. 3, 2014]

Background for High-K Gate

Silicon dioxide (SiO2) has been used to make for the gate of transistor for a long time. As the thickness of SiO2 is becoming thinner, the leakage of current is getting remarkable. According to Misra et al. [1], the leakage current density of 1.2nm–SiO2 gate is beyond 100A/m2 when applies 1V voltage. The situation is not allowed in most of application. However, when applying high-k materials, the capacitor of gate is becoming bigger than SiO2. In the other word, the gate can store more electric charge and the leakage current becomes less. The replacement of the SiO2 gate dielectric by high-k dielectric material is to improve the performance and simultaneously extend the scalability of Si MOSFETs.[2] HfSiO is one of high-k material which has better thermal stability is preferred to replace SiO2.

Posted on 3rd Feb. 2014 by Danyu Li and Saisai Wen

[1]. D. Misra, et al. (2005, Sumer). “High-k Gate Dielectrics” [Online]. Available: http://www.electrochem.org/dl/Interface/sum/sum05/IF08-05_Pg30-34.pdf. [Accessed: Jan. 1, 2014]

[2] Y. Taur, et al., “CMOS scaling into the nanometer regime,” Proc.IEEE, vol. 85, p. 486, Apr. 1997. 

Brief Information about Project 27

Our team is working on the Project 27 which is about high-k gate during the end of the first semester and the first five weeks of the second semester of year 2.

The group is consisted of three members -Danyu Li, Zhaojun Wei and Saisai Wen. All of the members are students form EEE department of University of Liverpool. Dr. Ivona Mitrovic, the supervisor of the project, is going to provide support with our project.

This project is designed to study the properties of high-k gate stack HfSiO (50%Hf), a new material may take the place of SiO₂ during transistors production. There are nine compulsory and one optional tasks are required to be accomplished.

This blog will first introduce the background of the project briefly and then narrate how those tasks are finished. If you have any questions about the project, please do not hesitate to ask us.

Posted by Saisai Wen on 3^rd Feb. 2014